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p roduct s pecification integrated circuits group LH28F320BFHE-PBTLEZ flash memory 32mbit (2mbitx16) (model number: lhf32fez) spec. issue date: september 13, 2004 spec no: el169103

lhf32fez ? handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufact ured for the following appli cation areas. when using the products covered herein for the equipment listed in paragr aph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, re dundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the follo wing equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and commen ts regarding the interpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products cove red herein to a sales representative of the company. rev. 2.44
lhf32fez 1 pa ge 48-lead tsop pinout................................................. 3 pin descriptions.......................................................... 4 simultaneous operation modes allowed with four planes .................................. 5 memory map .............................................................. 6 identifier codes and otp address for read operation ............................................. 7 identifier codes and otp address for read operation on partition configuration........ 7 otp block address map for otp program............... 8 bus operation............................................................. 9 command definitions .............................................. 10 functions of block lock and block lock-down..... 12 block locking state transitions upon command write................................................ 12 block locking state transitions upon wp#/acc transition ....................................... 13 status register definition......................................... 14 pag e extended status register definition ......................... 15 partition configuration register definition.............. 16 partition configuration ............................................. 16 1 electrical specifications......................................... 17 1.1 absolute maximum ratings ........................... 17 1.2 operating conditions ...................................... 17 1.2.1 capacitance .............................................. 18 1.2.2 ac input/output test conditions ............ 18 1.2.3 dc characteristics ................................... 19 1.2.4 ac characteristics - read-only operations......................... 21 1.2.5 ac characteristics - write operations ................................. 25 1.2.6 reset operations ...................................... 27 1.2.7 block erase, full chip erase, (page buffer) program and otp program performance.................... 28 2 related document information.............................. 29 3 package and packing specification ........................ 30 contents rev. 2.44
lhf32fez 2 LH28F320BFHE-PBTLEZ 32mbit (2mbit 16) page mode dual work flash memory 32m density with 16bit i/o interface high performance reads ? 60/25ns 8-word page mode configurative 4-plane dual work ? flexible partitioning ? read operations during block erase or (page buffer) program ? status register for each partition low power operation ? 2.7v read and write operations ? automatic power savings mode reduces i ccr in static mode enhanced code + data storage ? 5 s typical erase/program suspends otp (one time program) block ? 4-word factory-programmed area ? 4-word user-programmable area high performance program with page buffer ? 16-word page buffer ? 5 s/word (typ.) at 12v wp#/acc operating temperature -40 c to +85 c cmos process (p-type silicon substrate) flexible blocking architecture ? eight 4k-word parameter blocks ? sixty-three 32k-word main blocks ? bottom parameter location enhanced data protection features ? individual block lock and block lock-down with zero-latency ? all blocks are locked at power-up or device reset. ? block erase, full chip erase, (page buffer) word program lockout during power transitions automated erase/program algorithms ? 3.0v low-power 11 s/word (typ.) programming ? 12v no glue logic 9 s/word (typ.) production programming and 0.5s erase (typ.) cross-compatible command support ? basic command set ? common flash interface (cfi) extended cycling capability ? minimum 100,000 block erase cycles 48-lead tsop etox tm* flash technology not designed or rated as radiation hardened the product, which is 4-plane page mode dual work (simu ltaneous read while erase/program) flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.6v. its low voltage operation capability greatly extends battery life for portable applications. the product provides high performance asynchronous page mode. it allows code execution directly from flash, thus eliminating time consuming wait states. furthermore, its newly configurative partitioning architecture allows flexible dual work operation. the memory array block architecture utilizes enhanced data protection features, and provides separate parameter and main blocks that provide maximum flexibility for safe nonvolatile code and data storage. fast program capability is provided through the use of high speed page buffer program. special otp (one time program) block provides an ar ea to store permanent code such as a unique number. * etox is a trademark of intel corporation. rev. 2.44
lhf32fez 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-lead tsop standard pinout 12mm x 20mm top view a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we# rst# nc wp#/acc ry/by# a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 nc gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe# gnd ce# a 0 figure 1. 48-lead tsop (normal bend) pinout rev. 2.44
lhf32fez 4 table 1. pin descriptions symbol type name and function a 0 -a 20 input address inputs: inputs for addresses. 32m: a 0 -a 20 dq 0 -dq 15 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. data pins float to high- impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high (v ih ) deselects the device and reduces power consumption to standby levels. rst# input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rst# must be low during power-up/down. oe# input output enable: gates the devi ce?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of ce# or we# (whichever goes high first). wp#/acc input/ supply write protect: when wp#/acc is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and not locked-down. when wp#/acc is v ih , lock-down is disabled. applying 12v0.3v to wp#/acc provides fast erasing or fast programming mode. in this mode, wp#/acc is power supply pin. applying 12v0.3v to wp#/acc during erase/program can only be done for a maximum of 1,000 cycles on each block. wp#/ acc may be connected to 12v0.3v for a total of 80 hours maximum. use of this pin at 12v beyond these limits may reduce block cycling capability or cause permanent damage. ry/by# open drain output ready/busy#: indicates the status of the internal wsm (write state machine). when low, wsm is performing an internal operation (b lock erase, full chip erase, (page buffer) program or otp program). ry/by#-high z indicates that the wsm is ready for new commands, block erase is suspended and (page buffer) program is inactive, (page buffer) program is suspended, or the device is in reset mode. v cc supply device power supply (2.7v-3.6v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. rev. 2.44
lhf32fez 5 notes: 1. "x" denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write st ate machine) state - this allows a status register for each partition. only one partition can be erased or programmed at a time - no command queuing. commands must be written to an address within the block targeted by that command. table 2. simultaneous operation modes allowed with four planes (1, 2) if one partition is: then the modes allowed in the other partition is: read array read id/otp read status read query word program page buffer program otp program block erase full chip erase program suspend block erase suspend read array x x x x x x x x x read id/otp x x x x x x x x x read status x x x x x x x x x x x read query x x x x x x x x x word program x x x x x page buffer program xxxx x otp program x block erasexxxx full chip erase x program suspend xxxx x block erase suspend xxxx x x x rev. 2.44
lhf32fez 6 6 5 4 3 2 1 0 7 8 9 10 11 12 13 15 16 17 18 19 20 14 21 22 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh 23 24 25 26 27 28 29 31 32 33 34 35 36 30 37 38 32k-word 0f8000h - 0fffffh 32k-word 0f0000h - 0f7fffh 32k-word 0e8000h - 0effffh 32k-word 0e0000h - 0e7fffh 32k-word 0d8000h - 0dffffh 32k-word 0d0000h - 0d7fffh 32k-word plane1 (uniform plane) 0c8000h - 0cffffh 32k-word 0c0000h - 0c7fffh 32k-word 0b8000h - 0bffffh 32k-word 0b0000h - 0b7fffh 32k-word 0a8000h - 0affffh 32k-word 0a0000h - 0a7fffh 32k-word 098000h - 09ffffh 32k-word 090000h - 097fffh 32k-word 088000h - 08ffffh 32k-word 080000h - 087fffh 39 40 41 42 43 44 45 47 48 49 50 51 52 46 53 54 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word plane2 (uniform plane) 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 55 56 57 58 59 60 61 63 64 65 66 67 68 62 69 70 32k-word 1f8000h - 1fffffh 32k-word 1f0000h - 1f7fffh 32k-word 1e8000h - 1effffh 32k-word 1e0000h - 1e7fffh 32k-word 1d8000h - 1dffffh 32k-word 1d0000h - 1d7fffh 32k-word plane3 (uniform plane) 1c8000h - 1cffffh 32k-word 1c0000h - 1c7fffh 32k-word 1b8000h - 1bffffh 32k-word 1b0000h - 1b7fffh 32k-word 1a8000h - 1affffh 32k-word 1a0000h - 1a7fffh 32k-word 198000h - 19ffffh 32k-word 190000h - 197fffh 32k-word 188000h - 18ffffh 32k-word 180000h - 187fffh block number address range block number address range rev. 2.44 figure 2. memory map (bottom parameter)
lhf32fez 7 notes: 1. the address a 20 -a 16 are shown in below table for reading the manufacturer code, device code, device configuration code and otp data. 2. bottom parameter device has its parameter blocks in the plane0 (the lowest address). 3. block address = the beginning location of a block address within the partition to which the read identifier codes/otp command (90h) has been written. dq 15 -dq 2 are reserved for future implementation. 4. pcrc=partition configuration register code. 5. otp-lk=otp block lock configuration. 6. otp=otp block data. notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). 2. refer to table 12 for the partition configuration register. table 3. identifier codes and otp address for read operation code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 1 device code bottom parameter device code 0001h 00b5h 1, 2 block lock configuration code block is unlocked block address + 2 dq 0 = 0 3 block is locked dq 0 = 1 3 block is not locked-down dq 1 = 0 3 block is locked-down dq 1 = 1 3 device configuration code partition configuration register 0006h pcrc 1, 4 otp otp lock 0080h otp-lk 1, 5 otp 0081-0088h otp 1, 6 table 4. identifier codes and otp address for read operation on partition configuration (1) (32m-bit device) partition configuration register (2) address (32m-bit device) pcr.10 pcr.9 pcr.8 [a 20 -a 16 ] 0 0 0 00h 0 0 1 00h or 08h 0 1 0 00h or 10h 1 0 0 00h or 18h 0 1 1 00h or 08h or 10h 1 1 0 00h or 10h or 18h 1 0 1 00h or 08h or 18h 1 1 1 00h or 08h or 10h or 18h rev. 2.44
lhf32fez 8 rev. 2.44 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000088h [a 20 -a 0 ] (dq 15 -dq 2) figure 3. otp block address map for otp program (the area outside 80h~88h cannot be used.)
lhf32fez 9 rev. 2.44 notes: 1. see dc characteristics for v il or v ih voltages. 2. x can be v il or v ih . 3. rst# at gnd0.2v ensures the lowest power consumption. 4. command writes involving block erase, full chip erase, (page buffer) program or otp program are reliably executed when v cc =2.7v-3.6v. 5. refer to table 6 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. refer to appendix of lh28f320bf series for more information about query code. 8. ry/by# is v ol when the wsm (write state machine) is execu ting internal block eras e, full chip erase, (page buffer) program or otp program algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with program and page buf fer program inactive), (page buffer) program suspend mode, or reset mode. table 5. bus operation (1, 2) mode notes rst# ce# oe# we# address dq 0-15 ry/by# (8) read array 6 v ih v il v il v ih xd out x output disable v ih v il v ih v ih xhigh zx standby v ih v ih xx xhigh zx reset 3 v il xxx xhigh zhigh z read identifier codes/otp 6 v ih v il v il v ih see table 3 and table 4 see table 3 and table 4 x read query 6,7 v ih v il v il v ih see appendix see appendix x write 4,5,6 v ih v il v ih v il xd in x
lhf32fez 10 notes: 1. bus operations are defined in table 5. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see table 3 and table 4). qa=query codes address. refer to appendix of lh28f320bf series for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see figure 3). pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes. (see table 3 and table 4). qd=data read from query database. refer to appendix of lh28f320bf series for details. srd=data read from status register. see table 10 and table 11 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. od=data within otp block. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within otp block (see table 3 and table 4). the read query command is available for read ing cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program can not be executed when the select ed block is locked. unlocked block can be erased or programmed when rst# is v ih . table 6. command definitions (11) command bus cycles req?d notes first bus cycle second bus cycle oper (1) addr (2) data oper (1) addr (2) data (3) read array 1 write pa ffh read identifier codes/otp 2 4 write pa 90h read ia or oa id or od read query 2 4 write pa 98h read qa qd read status register 2 write pa 70h read pa srd clear status register 1 write pa 50h block erase 2 5 write ba 20h write ba d0h full chip erase 2 5,9 write x 30h write x d0h program 2 5,6 write wa 40h or 10h write wa wd page buffer program 4 5,7 write wa e8h write wa n-1 block erase and (page buffer) program suspend 1 8,9 write pa b0h block erase and (page buffer) program resume 1 8,9 write pa d0h set block lock bit 2 write ba 60h write ba 01h clear block lock bit 2 10 write ba 60h write ba d0h set block lock-down bit 2 write ba 60h write ba 2fh otp program 2 9 write oa c0h write oa od set partition configuration register 2 write pcrc 60h write pcrc 04h rev. 2.44
lhf32fez 11 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, input the program sequential address and write data of "n" times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). refer to appendix of lh28f320bf series for details. 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp#/acc is v il . when wp#/acc is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 2.44
lhf32fez 12 notes: 1. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 2. erase and program are general terms, respectivel y, to express: block erase, full chip erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are no t locked-down, that is, [001] (wp#/acc=0) or [101] (wp#/acc=1), regardle ss of the states before power-off or reset operation. 4. when wp#/acc is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock function which is different from those described above. notes: 1. "set lock" means set block lock bit comma nd, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp#/acc is not changed and fixed v il or v ih . table 7. functions of block lock (5) and block lock-down current state erase/program allowed (2) state wp#/acc dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 001locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 101locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no table 8. block locking state transitions upon command write (4) current state result after lock command written (next state) state wp#/acc dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change rev. 2.44
lhf32fez 13 rev. 2.44 notes: 1. "wp#/acc=0 1" means that wp#/acc is driven to v ih and "wp#/acc=1 0" means that wp#/acc is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp#/acc is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 9. block locking state transitions upon wp#/acc transition (4) previous state current state result after wp#/acc transition (next state) state wp#/acc dq 1 dq 0 wp#/acc=0 1 (1) wp#/acc=1 0 (1) - [000] 0 0 0 [100] - - [001] 0 0 1 [101] - [110] (2) [011] 0 1 1 [110] - other than [110] (2) [111] - - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] -[110]110 - [011] (3) - [111] 1 1 1 - [011]
lhf32fez 14 table 10. status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pbpops wpaccs pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (page buffer) program and otp program status (pbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = wp#/acc status (wpaccs) 1 = v cc +0.4v < wp#/acc < 11.7v detect, operation abort 0 = wp#/acc ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 or ry/by# to determine block erase, full chip erase, (page buffer) program or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of wp#/acc level. the wsm interrogates and indicates the wp#/acc level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accu rate feedback when wp#/ acc v acch . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are rese rved for future use and should be masked out when polling the status register. rev. 2.44
lhf32fez 15 rev. 2.44 table 11. extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7="1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register.
lhf32fez 16 rev. 2.44 table 12. partition configuration register definition rrrrrpc2pc1pc0 15 14 13 12 11 10 9 8 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0-1 and plane2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in a top parameter device) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respec- tively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: after power-up or device reset, pcr10-8 (pc2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. see figure 4 for the detail on partition configuration. pcr.15-11 and pcr.7-0 are reserved for future use and should be masked out when checking the partition configuration register. plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 partition2 partition3 partition2 partition2 partition1 partition2 000 001 010 100 011 110 101 111 pc2 pc1pc0 partitioning for dual work partitioning for dual work pc2 pc1pc0 figure 4. partition configuration
lhf32fez 17 1 electrical specifications 1.1 absolute maximum ratings * operating temperature during read, erase and program ...-40 c to +85 c (1) storage temperature during under bias............................... -40 c to +85 c during non bias................................ -65 c to +125 c voltage on any pin (except v cc and wp#/acc)... -0.5v to v cc +0.5v (2) v cc supply voltage ........................... -0.2v to +3.9v (2) wp#/acc supply voltage ......... -0.2v to +12.6v (2, 3, 4) output short circuit current ........................... 100ma (5) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and wp#/acc pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on wp#/acc may overshoot to +13.0v for periods <20ns. 4. wp#/acc erase/program voltage is normally 2.7v- 3.6v. applying 11.7v-12.3v to wp#/acc during erase/program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. wp#/acc may be connected to 11.7v-12.3v for a total of 80 hours maximum. 5. output shorted for no more than one second. no more than one output shorted at a time. rev. 2.44 1.2 operating conditions notes: 1. see dc characteristics tables for voltage range-specific specification. 2. applying wp#/acc=11.7v-12.3v during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. a perman ent connection to wp#/acc=11.7v-12.3v is not allowed and can cause damage to the device. parameter symbol min. typ. max. unit notes operating temperature t a -40 +25 +85 c v cc supply voltage v cc 2.7 3.0 3.6 v 1 wp#/acc voltage when used as a logic control v il -0.2 0.4 v 1 v ih 2.4 v cc + 0.4 v wp#/acc supply voltage v acch 11.7 12 12.3 v 1, 2 main block erase cycling: wp#/acc=v il or v ih 100,000 cycles parameter block erase cycling: wp#/acc=v il or v ih 100,000 cycles main block erase cycling: wp#/acc=v acch , 80 hrs. 1,000 cycles parameter block erase cycling: wp#/acc=v acch , 80 hrs. 1,000 cycles maximum wp#/acc hours at v acch 80 hours
lhf32fez 18 test points v cc /2 v cc /2 input v cc 0.0 output ac test inputs are driven at v cc (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v cc /2. input rise and fall times (10% to 90%) < 5ns. worst case speed conditions are when v cc =v cc (min).

! " figure 6. transient equivalent testing load circuit rev. 2.44 table 13. configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 50 1.2.2 ac input/output test conditions 1.2.1 capacitance (1) (t a = + 25 c, f=1mhz) note: 1. sampled, not 100% tested. parameter symbol condition min. typ. max. unit input capacitance c in v in =0.0v 47pf wp#/acc input capacitance c in v in =0.0v 18 22 pf output capacitance c out v out =0.0v 610pf figure 5. transient input/output reference waveform for v cc =2.7v-3.6v
lhf32fez 19 rev. 2.44 1.2.3 dc characteristics v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions i li input load current 1 -1.0 +1.0 a v cc =v cc max., v in /v out =v cc or gnd i lo output leakage current 1 -1.0 +1.0 a i ccs v cc standby current 1,7 4 20 a v cc =v cc max., ce#=rst#= v cc 0.2v, wp#/acc=v cc or gnd i ccas v cc automatic power savings current 1,3 4 20 a v cc =v cc max., ce#=gnd0.2v, wp#/acc=v cc or gnd i ccd v cc reset power-down current 1420 a rst#=gnd0.2v i ccr average v cc read current normal mode 1,6 15 25 ma v cc =v cc max., ce#=v il , oe#=v ih , f=5mhz average v cc read current page mode 8 word read 1,6 5 10 ma i ccw v cc (page buffer) program current 1,4,6 20 60 ma wp#/acc=v il or v ih 1,4,6 10 20 ma wp#/acc=v acch i cce v cc block erase, full chip erase current 1,4,6 10 30 ma wp#/acc=v il or v ih 1,4,6 4 10 ma wp#/acc=v acch i ccws i cces v cc (page buffer) program or block erase suspend current 1,2,6 10 200 a ce#=v ih i accs i accr wp#/acc standby or read current 1,5,6 2 5 a wp#/acc v cc i accw wp#/acc (page buffer) program current 1,4,5,6 2 5 a wp#/acc=v il or v ih 1,4,5,6 10 30 ma wp#/acc=v acch i acce wp#/acc block erase, full chip erase current 1,4,5,6 2 5 a wp#/acc=v il or v ih 1,4,5,6 5 15 ma wp#/acc=v acch i accws wp#/acc (page buffer) program suspend current 1,5,6 2 5 a wp#/acc=v il or v ih 1,5,6 10 200 a wp#/acc=v acch i acces wp#/acc block erase suspend current 1,5,6 2 5 a wp#/acc=v il or v ih 1,5,6 10 200 a wp#/acc=v acch
lhf32fez 20 notes: 1. all currents are in rms unless otherwise noted . typical values are the reference values at v cc =3.0v and t a =+25 c unless v cc is specified. 2. i ccws and i cces are specified with the device de-selected. if read or (page buffer) program is executed while in block erase suspend mode, the device?s current draw is the sum of i cces and i ccr or i ccw . if read is executed while in (page buffer) program suspend mode, the device?s current draw is the sum of i ccws and i ccr . 3. the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t av q v ) provide new data when addresses are changed. 4. sampled, not 100% tested. 5. applying 12v0.3v to wp#/acc provides fast erasing or fast programming mode. in this mode, wp#/acc is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. use similar power supply trace widths and layout co nsiderations given to the v cc power bus. applying 12v0.3v to wp#/acc during erase/program can only be done for a maximum of 1,000 cycles on each block. wp#/acc may be connected to 12v0.3v for a total of 80 hours maximum. 6. the operating current in dual work is the sum of th e operating current (read, eras e, program) in each plane. 7. includes ry/by#. v il input low voltage 4 -0.4 0.4 v v ih input high voltage 4 2.4 v cc + 0.4 v v ol output low voltage 4,7 0.2 v v cc =v cc min., i ol =100 a v oh output high voltage 4 v cc -0.2 v v cc =v cc min., i oh =-100a v acch wp#/acc during block erase, full chip erase, (page buffer) program or otp program operations 5 11.7 12 12.3 v v lko v cc lockout voltage 1.5 v v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions rev. 2.44 dc characteristics (continued)
lhf32fez 21 1.2.4 ac characteristics - read-only operations (1) notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. sampled, not 100% tested. 3. oe# may be delayed up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . 4. address setup time (t av e l , t av g l ) is defined from the falling edge of ce# or oe# (whichever goes low last). 5. address hold time (t elax , t glax ) is defined from the falling edge of ce# or oe# (whichever goes low last). 6. specifications t av e l , t av g l , t elax , t glax and t ehel , t ghgl for read operations apply to only status register read operations. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav read cycle time 60 ns t avqv address to output delay 60 ns t elqv ce# to output delay 3 60 ns t apa page address access time 25 ns t glqv oe# to output delay 3 20 ns t phqv rst# high to output delay 150 ns t ehqz , t ghqz ce# or oe# to output in high z, whichever occurs first 2 20 ns t elqx ce# to output in low z 2 0 ns t glqx oe# to output in low z 2 0 ns t oh output hold from first occurring address, ce# or oe# change 2 0 ns t av e l , t avgl address setup to ce#, oe# going low for reading status register 4, 6 10 ns t elax , t glax address hold from ce#, oe# going low for reading status register 5, 6 30 ns t ehel , t ghgl ce#, oe# pulse width high for reading status register 615 ns rev. 2.44
lhf32fez 22 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 20-0 dq 15-0 ce# oe# we# rst# high z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax t oh figure 7. ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code rev. 2.44
lhf32fez 23 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv high z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (w) (g) (e) (a) a 20-3 v ih v il (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address valid address valid address valid address valid output valid output valid output valid output valid address t avav figure 8. ac waveform for asynchronous 4-word page mode read operations from main blocks or parameter blocks rev. 2.44
lhf32fez 24 rev. 2.44 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv v ih v il v ih v il v ih v il v ih v il v ih v il (p) (w) (g) (e) (a) a 20-3 (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address t avav v ih v il valid address valid address valid address valid address high z v oh v ol valid output valid output valid output valid output valid address valid address valid address valid address valid output valid output valid output valid output figure 9. ac waveform for asynchronous 8-word page mode read operations from main blocks or parameter blocks
lhf32fez 25 rev. 2.44 1.2.5 ac characteristics - write operations (1), (2) notes: 1. the timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and otp program operations are the same as during read-onl y operations. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of ce# or we# (whichever goes low last) to the rising edge of ce# or we# (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of ce# or we# (whichever goes high first) to the falling edge of ce# or we# (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. t whr0 (t ehr0 ) after the read query or read identifier codes/otp command=t avqv +100ns. 7. refer to table 6 for valid address and data for block erase, full chip erase, (page buffer) program, otp program or lock bit configuration. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav write cycle time 60 ns t phwl (t phel ) rst# high recovery to we# ( ce# ) going low 3 150 ns t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 0 ns t wlwh (t eleh ) we# (ce#) pulse width 4 45 ns t dvwh (t dveh ) data setup to we# (ce#) going high 7 40 ns t av w h (t av e h ) address setup to we# (ce#) going high 7 45 ns t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns t whdx (t ehdx ) data hold from we# (ce#) high 0 ns t whax (t ehax ) address hold from we# (ce#) high 0 ns t whwl (t ehel ) we# (ce#) pulse width high 5 15 ns t shwh (t sheh ) wp#/acc high setup to we# (ce#) going high wp#/acc=v ih 3 0 ns wp#/acc=v acch 200 t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp#/acc high hold from valid srd, ry/by# high z 3 0 ns t whr0 (t ehr0 ) we# (ce#) high to sr.7 going "0" 3, 6 t avqv +50 ns t whrl (t ehrl ) we# (ce#) high to ry/by# going low 3 100 ns
lhf32fez 26 t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t whqv1,2,3 (t ehqv1,2,3 ) t qvsl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il (d/q) (w) (g) (e) (a) notes 5, 6 a 20-0 dq 15-0 v ih v il (p) rst# ce# oe# we# v ih v il (s) wp# (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, oe# and ce# must be driven active, and we# de-asserted. ("1") v ol (r) ry/by# (sr.7) high z ("0") (t whr0 (t ehr0 )) t whrl (t ehrl ) notes 5, 6 figure 10. ac waveform for write operations rev. 2.44 wp#/acc (s) v ih , v acch
lhf32fez 27 abort complete t plph t plph t 2vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst# rising timing rst# rst# v il v ih v il v ih v cc gnd v cc (min) rst# v il v ih sr.7="1" v oh v ol (d/q) dq 15-0 valid output high z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high z v oh v ol (d/q) dq 15-0 valid output high z t phqv t vhqv notes: 1. a reset time, t phqv , is required from the later of sr.7 (ry/by#) going "1" (high z) or rst# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst# asserted while a block erase, full chip erase, (page buffer) program or otp program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. reset ac specifications (v cc =2.7v-3.6v, t a =-40 c to +85 c) symbol parameter notes min. max. unit t plph rst# low to reset during read (rst# should be low during power-up.) 1, 2, 3 100 ns t plrh rst# low to reset during erase or program 1, 3, 4 22 s t 2vph v cc 2.7v to rst# high 1, 3, 5 100 ns t vhqv v cc 2.7v to output delay 31ms figure 11. ac waveform for reset operations rev. 2.44 1.2.6 reset operations
lhf32fez 28 rev. 2.44 1.2.7 block erase, full chip erase, (page buffer) program and otp program performance (3) notes: 1. typical values measured at v cc =3.0v, wp#/acc=3.0v or 12v, and t a =+25 c. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 4. a latency time is required from writing suspend command (we# or ce# going high) until sr.7 going "1" or ry/by# going high z. 5. if the interval time from a block erase resume comma nd to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes page buffer command is used or not used wp#/acc=v il or v ih (in system) wp#/acc=v acch (in manufacturing) unit min. typ. (1) max. (2) min. typ. (1) max. (2) t wpb 4k-word parameter block program time 2 not used 0.05 0.3 0.04 0.12 s 2 used 0.03 0.12 0.02 0.06 s t wmb 32k-word main block program time 2 not used 0.38 2.4 0.31 1.0 s 2 used 0.24 1.0 0.17 0.5 s t whqv1 / t ehqv1 word program time 2 not used 11 200 9 185 s 2 used 7 100 5 90 s t whov1 / t ehov1 otp program time 2 not used 36 400 27 185 s t whqv2 / t ehqv2 4k-word parameter block erase time 2 - 0.3 4 0.2 4 s t whqv3 / t ehqv3 32k-word main block erase time 2 - 0.6 5 0.5 5 s full chip erase time 2 40 350 33 350 s t whrh1 / t ehrh1 (page buffer) program suspend latency time to read 4- 510 510 s t whrh2 / t ehrh2 block erase suspend latency time to read 4- 520 520 s t eres latency time from block erase resume command to block erase suspend command 5-500 500 s
lhf32fez 29 rev. 2.44 2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales offices. document no. document name fum00701 lh28f320bf series appendix

lh28f320bfxx-xxxxxx flash memory errata 1. ac characteristics problem the table below summarizes the ac characteristics. ac characteristics - write operations workaround system designers should consider these specifications. status this is intended to be fixed in future devices. v cc =2.7v-3.6v page symbol parameter min. max. unit 25 t avav write cycle time 75 ns 25 t wlwh (t eleh ) we# (ce#) pulse width t avav =75ns 50 ns 25 t whwl (t ehel ) we# (ce#) pulse width high 25 ns 021114 i
rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph v cc gnd v cc (min) rp# v il v ih (p) t phqv ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) v oh v ol (d/q) data high z valid output t vr t f t elqv t f t glqv (a) address valid (rst#) t r or t f address v il v ih t avqv t r or t f t r t r
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit
v a-3 status register read operations if ac timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit sr.15 instead of sr.7 to determine when the erase or program operation has been completed. figure a-3-1. example of checking the status register (in this example, the device contains four partitions.) table a-3-1. status register definition (sr.15 and sr.7) sr.15 = write state machine status: (dq 15 ) 1 = ready in all partitions 0 = busy in any partition sr.7 = write state machine status for each partition: (dq 7 ) 1 = ready in the addressed partition 0 = busy in the addressed partition notes: sr.15 indicates the status of wsm (write state machine). if sr.15="0", erase or program operation is in progress in any partition. sr.7 indicates the status of the partition. if sr.7="0", erase or program operation is in progress in the addressed partition. even if the sr.7 is "1", the wsm may be occupied by the other partition. v ih v il v ih v il v ih v il v ih v il (d/q) (w) (e) (a) address dq 15-0 ce# we# valid address within partition 0 valid command "1" "0" (r) sr.15 ( partition 0 ) "1" "0" (r) sr.7 ( partition 0 ) "1" "0" (r) sr.15 ( partition 1 ) "1" "0" (r) sr.7 ( partition 1 ) "1" "0" (r) sr.15 ( partition 2 ) "1" "0" (r) sr.7 ( partition 2 ) "1" "0" (r) sr.15 ( partition 3 ) "1" "0" (r) sr.7 ( partition 3 ) plane1 plane0 plane2 plane3 partition0 partition1 partition2 partition3 operation to partition 0 t whr0 (t ehr0 ) valid address within partition 2 valid command operation to partition 2 t whr0 (t ehr0 ) check sr.15 instead of sr.7 in partition 0 check sr.15 instead of sr.7 in partition 2 021211
s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5

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